1. Field of Art
This disclosure relates to the art of electronic design automation (EDA), and more specifically to an automated design process and chip description system.
2. Description of the Related Art
Battery life is a critical factor for success of a mobile product. Hence every silicon chip now provides low power functionality as a method to extend the battery life. Low power functionality may be provided in practice by shutting down part of the chip to save leakage power and designing the chip to have multiple voltage domains where different domains can operate at different power states to provide either performance (at the price of high power consumption) or low power consumption (with a lower level of performance).
When a chip has multiple functional blocks, many of the blocks can be switched off or while other blocks can be powered at a variety of different power levels. Clearly, at any instance, the number of possible combinations of different functional blocks turning off or transitioning to a voltage state can be very large in modern chips.
Since defects in the low power functionality can cause chips to malfunction, every chip need to be verified to ensure that for all possible power states (that is, the combination of functional blocks switched off or set to a low voltage state) to ensure that the chip behaves correctly. One way to perform the verification is to identify all of the circuit paths in a chip which are involved in crossing from one power domain. The actual verification process includes verifying that the circuit paths function correctly for all possible combinations of voltage states for each power domain. However, in some circuit configurations, functional errors may be indicated for crossover paths for voltage state combinations that do not occur during operation of the final circuit. Hence, the unnecessary analysis of such crossover paths, with each path having large number of elements will be expensive in terms of runtime and misleading to the users, increasing verification effort.
What is needed is an improved concept for performing a functional verification of a circuit description that reduces verification effort.